1. Field of the Invention
The present invention relates to a static RAM (SRAM) and, more particularly, to transistors constituting the memory cells of an SRAM.
2. Description of the Related Art
Today, a high resistance load type SRAM is a predominant type of SRAM and has memory cells each being implemented by N type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and high resistance loads. For the microstructure of this type of SRAM, transistors constituting a memory cell, decoder circuits and other circuits are provided with a minimum size prescribed by design standards. However, a decrease in the size of transistors has aggravated the influence of the short channel effect of transistors. Particularly, in the memory cells, the subthreshold current (leak current) of drive transistors is increased by the short channel effect, deteriorating the data holding characteristic of the memory cells. This problem has customarily been solved by reducing the load resistance so as to increase the load current.
However, an increase in load current directly translates into an increase in the data holding current of each memory cell. This degrades the merit of the SRAM that power consumption in a waiting state is small.